Many digital systems have multiple dock domains. Thus, when signals move from one clock domain to another, they must be synchronized to avoid metastability and synchronization failure. Typically, signals passing between clock domains are synchronized with a periodic clock using asynchronous first-in, first-outs (FIFOs). A significant area overhead is incurred for the FIFO memory. The FIFOs also add several cycles of delay as the Gray-coded input and output pointers of the FIFO must be synchronized through multiple flip-flops to reliably transmit the signals across clock domains.
There is thus a need for addressing these and/or other issues associated with the prior art.